Inventor · Austin, TX, US

Jun Sawada

66Patents
8h-index
52Co-inventors
81Inventor score

Filing activity: Jun 29, 1990 → Oct 13, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US10621489B2 Massively parallel neural inference computing elements Electricity 23 Active
US9852006B2 Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits Physics 12 Active
US5103739A Apparatus for tracking an overhead line and automatically moving around obstacles on the line Electricity 12 Expired
US9992057B2 Yield tolerance in a neurosynaptic system Electricity 12 Active
US8181134B2 Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design Physics 11 Active
US9244124B2 Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs Physics 11 Active
US9747545B2 Self-timed, event-driven neurosynaptic core controller Physics 9 Active
US8397187B2 Verifying the error bound of numerical computation implemented in computer systems Physics 8 Active
US7529371B2 Replaceable sequenced one-time pads for detection of cloned service client Electricity 7 Expired
US9924490B2 Scaling multi-core neurosynaptic networks across chip boundaries Electricity 6 Active
US6675182B1 Method and apparatus for performing rotate operations using cascaded multiplexers Physics 6 Expired
US9984324B2 Dual deterministic and stochastic neurosynaptic core circuit Physics 6 Active
US9588937B2 Array of processor core circuits with reversible tiers Physics 5 Active
US10410109B2 Peripheral device interconnections for neurosynaptic systems Physics 5 Active
US9558443B2 Dual deterministic and stochastic neurosynaptic core circuit Physics 4 Active
US7272624B2 Fused booth encoder multiplexer Physics 4 Expired
US9886662B2 Converting spike event data to digital numeric data Physics 4 Active
US9940302B2 Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array Electricity 4 Active
US10452540B2 Memory-mapped interface for message passing computing systems Physics 3 Active
US7383480B2 Scanning latches using selecting array Physics 3 Expired
US8229992B2 Fused booth encoder multiplexer Physics 3 Active
US10102474B2 Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network Physics 3 Active
US10454759B2 Yield tolerance in a neurosynaptic system Electricity 3 Active
US10650301B2 Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation Physics 2 Active
US9601921B2 Tie-off circuit with output node isolation for protection from electrostatic discharge (ESD) damage Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.