Characterization and reduction of variation for integrated circuits
US7383521B2 · kind B2 · utility
325Cited by
69References
96Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Dec 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.