Exception handling control in a secure processing system
US7383587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Jun 3, 2008 |
| Priority date | — |
| Expiry date | Oct 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45587
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.