Fin field effect transistors with low resistance contact structures
US7385237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2005 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Feb 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
Abstract
Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.