Shielded gate field effect transistor with improved inter-poly dielectric
US7385248B2 · kind B2 · utility
64Cited by
297References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 9, 2005 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Aug 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD). The IPD comprises a conformal layer of dielectric and a thermal oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.