Semiconductor memory device and semiconductor integrated circuit device
US7385870B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 20, 2007 |
| Grant date | Jun 10, 2008 |
| Priority date | — |
| Expiry date | Jun 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.