Substrate isolation in integrated circuits
US7387942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Feb 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.