Content based yield prediction of VLSI designs
US7389480B2 · kind B2 · utility
1Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | May 9, 2005 |
| Grant date | Jun 17, 2008 |
| Priority date | — |
| Expiry date | Jul 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.