SONOS embedded memory with CVD dielectric

US7390718B2 · kind B2 · utility

Assignee

• TOWER PARTNERS SEMICONDUCTOR CO., LTD. · IL

Inventors

• Yakov Roizin · Afula, IL
• Zmira Shterenfeld-Lavie · Jerusalem, IL
• Itzhak Edrei · Haifa, IL

Key dates

• Filing date: Feb 20, 2004
• Grant date: Jun 24, 2008
• Expiry date: Oct 25, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

An embedded semiconductor memory is fabricated by: forming diffusion bit line regions in a semiconductor substrate; then thermally oxidizing the upper surface of the substrate, thereby forming a bottom oxide layer over the substrate and simultaneously forming bit line oxide regions over each of the diffusion bit line regions; and then forming an intermediate dielectric layer (e.g., silicon nitride), over the bottom oxide layer and the bit line oxide regions. CMOS well implants are then performed in a CMOS section of the device through the silicon nitride layer and bottom oxide layer. The silicon nitride layer and bottom oxide layer are then removed in the CMOS section, and a top dielectric layer, such as a high-temperature oxide or a high-k dielectric, is deposited. The top dielectric layer completes a memory stack of the memory device, and forms a gate dielectric layer of a high voltage transistor in the CMOS section.