Method of manufacturing a semiconductor device having a dual gate structure
US7390719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2006 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Nov 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.