LDMOS transistor device employing spacer structure gates
US7391080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Oct 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated LDMOS transistor comprises a semiconductor substrate (11), an LDMOS gate region (17), LDMOS source (14) and drain (15) regions, and a channel region (13) arranged beneath the LDMOS gate region, where the channel region interconnects the LDMOS source and drain regions. The LDMOS gate region comprises first (18a) and second (18b) gate insulation layer regions, a centrally located gate-dividing insulation region (19) provided between the first and second gate insulation layer regions, and first (20a) and second (20b) individual gate conducting layer regions, each being provided on top of a respective one of the first and second gate insulation layer regions, and each being an etched outside spacer region at the centrally located insulation layer region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.