LDMOS transistor device, integrated circuit, and fabrication method thereof

US7391084B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Torkel Arnborg · Stockholm, SE
• Ulf Smith · Huddinge, SE

Key dates

• Filing date: Jun 17, 2004
• Grant date: Jun 24, 2008
• Expiry date: Nov 5, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/65

Abstract

An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4) and drain (5, 7) regions, and a channel (6; 12) arranged beneath the LDMOS gate region, the channel interconnecting the LDMOS source and drain regions and having a laterally graded doping concentration. In order to obtain a lower parasitic capacitance coupling from the gate semiconductor region, the gate semiconductor layer region is provided with a laterally graded net doping concentration (P+N+; N+N−). A method for fabrication of the inventive LDMOS transistor device is further disclosed.