Distributed memory in field-programmable gate array integrated circuit devices
US7391236B2 · kind B2 · utility
6Cited by
18References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2005 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.