Paul Leventis
49Patents
11h-index
45Co-inventors
75Inventor score
Filing activity: Jan 25, 2002 → Dec 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7180324B2 | Redundancy structures and methods in a programmable logic device | Electricity | 37 | Expired |
| US6965249B2 | Programmable logic device with redundant circuitry | Electricity | 24 | Expired |
| US7253660B1 | Multiplexing device including a hardwired multiplexer in a programmable logic device | Electricity | 21 | Expired |
| US6605962B2 | PLD architecture for flexible placement of IP function blocks | Electricity | 21 | Expired |
| US6937064B1 | Versatile logic element and logic array block | Electricity | 21 | Expired |
| US6630842B1 | Routing architecture for a programmable logic device | Electricity | 18 | Expired |
| US7084665B1 | Distributed random access memory in a programmable logic device | Electricity | 14 | Expired |
| US6826741B1 | Flexible I/O routing resources | Electricity | 14 | Expired |
| US11369873B2 | Methods and systems for rendering and encoding content for online interactive gaming sessions | Physics | 12 | Active |
| US7218133B2 | Versatile logic element and logic array block | Electricity | 11 | Expired |
| US7400167B2 | Apparatus and methods for optimizing the performance of programmable logic devices | Electricity | 11 | Expired |
| US6653862B2 | Use of dangling partial lines for interfacing in a PLD | Electricity | 10 | Expired |
| US8103975B2 | Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage | Electricity | 9 | Active |
| US9576095B1 | Partial reconfiguration compatibility detection in an integrated circuit device | Physics | 9 | Active |
| US7983880B1 | Simultaneous switching noise analysis using superposition techniques | Physics | 8 | Active |
| US8201129B2 | PLD architecture for flexible placement of IP function blocks | Electricity | 8 | Active |
| US6970014B1 | Routing architecture for a programmable logic device | Electricity | 8 | Expired |
| US7861190B1 | Power-driven timing analysis and placement for programmable logic | Physics | 7 | Active |
| US7644386B1 | Redundancy structures and methods in a programmable logic device | Electricity | 7 | Active |
| US7391236B2 | Distributed memory in field-programmable gate array integrated circuit devices | Electricity | 6 | Expired |
| US7058920B2 | Methods for designing PLD architectures for flexible placement of IP function blocks | Electricity | 5 | Expired |
| US7432734B2 | Versatile logic element and logic array block | Electricity | 5 | Active |
| US7236633B1 | Data compression and decompression techniques for programmable circuits | Electricity | 5 | Expired |
| US8443321B1 | Pessimism removal in the modeling of simultaneous switching noise | Physics | 5 | Active |
| US7656191B2 | Distributed memory in field-programmable gate array integrated circuit devices | Electricity | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.