2-transistor floating-body dram
US7391640B2 · kind B2 · utility
40Cited by
11References
43Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 10, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.