Non-volatile memory in CMOS logic process and method of operation thereof
US7391647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2006 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in a second n-type region (separate from the first n-type region), and an NMOS programming transistor located in a p-type region. The floating gate electrode is a continuous electrode which extends over the active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor. Various array connections are provided for implementing arrays using this NVM cell. The PMOS access transistor and NMOS programming transistor can be replaced with an NMOS access transistor and a PMOS erase transistor, respectively, in an alternate embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.