Apparatus and method for reducing the latency of sum-addressed shifters
US7392270B2 · kind B2 · utility
3Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Aug 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.