Method to operate cache-inhibited memory mapped commands to access registers
US7392350B2 · kind B2 · utility
2Cited by
5References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 10, 2005 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Feb 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.