Method and apparatus for testing DRAM memory chips in multichip memory modules
US7392443B2 · kind B2 · utility
8Cited by
9References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 2004 |
| Grant date | Jun 24, 2008 |
| Priority date | — |
| Expiry date | Nov 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for testing memory cells of a DRAM memory chip arranged together with a nonvolatile memory chip in a multichip memory module. The multichip memory module may be incorporated in an application apparatus, in particular in a mobile telephone or a notebook. One embodiment provides a method for the DRAM memory chip to be subjected to a self-test, during which the functionality of the memory cells is checked, in a time in which the memory cells of the DRAM memory chip are not accessed in an operative operating mode of the application apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.