Capping of metal interconnects in integrated circuit electronic devices
US7393781B2 · kind B2 · utility
10Cited by
44References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2007 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Sep 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.