Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same
US7394152B2 · kind B2 · utility
36Cited by
5References
5Claims
0Family size
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Key dates
| Filing date | Nov 13, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.