Built-in self test for system in package
US7394272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Jan 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.