Patent · US Active

Bit line dummy core-cell and method for producing a bit line dummy core-cell

US7394682B2 · kind B2 · utility

3Cited by

3References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Martin Ostermayr · Straubing, DE
Christophe Chanussot · Antibes, FR
Vincent Gouin · Mandelieu-la-Napoule, FR
Alexander Olbrich · Höhenkirchen-Siegertsbrunn, DE

Key dates

Filing date	Oct 25, 2006
Grant date	Jul 1, 2008
Priority date	—
Expiry date	Oct 25, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/413
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.