Method for column redundancy using data latches in solid-state memories
US7394690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.