Flash memory device with NAND architecture with reduced capacitive coupling effect
US7394694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Dec 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.