Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread
US7395418B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2005 |
| Grant date | Jul 1, 2008 |
| Priority date | — |
| Expiry date | Feb 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for improving the performance of a system that supports simultaneous multi-threading (SMT). When a first thread encounters a halt sequence, the system starts a transactional memory operation by generating a checkpoint and entering a transactional-execution mode. Next, the system loads from a mailbox address associated with the halt sequence. The system then stalls execution of the first thread, so that the first thread does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads. To terminate the halt sequence, a second thread stores to the mailbox address, which causes a transactional-memory mechanism within the processor to detect an interference with the previous load from the mailbox address by the first thread and which causes the first thread to exit from the halt sequence. The system then continues executing instructions following the halt sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.