Semiconductor structure including silicide regions and method of making same
US7396767B2 · kind B2 · utility
24Cited by
48References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2004 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Jul 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.