Method for fabricating semiconductor device having capacitor
US7396772B2 · kind B2 · utility
3Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2006 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Oct 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.