Gate electrode architecture for improved work function tuning and method of manufacture
US7397090B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2005 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Aug 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
A method of forming gate electrodes having different work functions includes forming a first well of a first conductivity type and a second well of a second conductivity type. Subsequently, a gate dielectric layer is deposited over the first and second wells. A multi-layer stack comprising two or more thin metal/metal nitride layers is next formed over the first well. A thick metal/metal nitride layer is formed over the multi-layer stack to form the first gate electrode. The thick metal/metal nitride layer is also formed over the gate dielectric layer portion extending over the second well, thereby forming the second gate electrode. The first and second electrodes are then annealed, and thereafter exhibit different work functions as desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.