Method and apparatus for statistical CMOS device characterization
US7397259B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.