Semiconductor memory device for testing redundancy cells
US7397715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2006 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Aug 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells. This increases the reliability of a repair operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.