Circuit for and method of realigning data
US7398334B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2004 |
| Grant date | Jul 8, 2008 |
| Priority date | — |
| Expiry date | Sep 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.