Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed
US7399670B2 · kind B2 · utility
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3References
19Claims
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Key dates
| Filing date | Jul 18, 2005 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Aug 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.