Formation of deep trench airgaps and related applications
US7400024B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2006 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.