Integrated circuit testing methods using well bias modification

US7400162B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Anne Elizabeth Gattiker · Austin, US
• David A. Grosch · Burlington, US
• Marc D. Knox · Mechanicsville, US
• Franco Motika · Hopewell Junction, US
• Phil Nigh · Williston, US
• Jody Van Horn · Underhill, US
• Paul S. Zuchowski · Williston, US

Key dates

• Filing date: Feb 20, 2003
• Grant date: Jul 15, 2008
• Expiry date: Feb 20, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/275
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.