NROM memory device with enhanced endurance
US7400538B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2006 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Nov 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable erase state is detected, the erase pulse magnitude is incrementally increased to compensate for the increasing parasitic electrons. When a predetermined maximum drain voltage is reached, the negative gate refresh voltage is applied to refresh the ONO structure, and the drain voltage is reset to an initial state. A novel NROM cell uses a P+ doped polysilicon gate or Top Oxide produced with a high-k dielectric (Alumina) to facilitate blocking the injection of gate electrons, and the Bottom Oxide thickness is selectively thinned to increase hole injection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.