Parallel Processor efficiently executing variable instruction word
US7401204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2000 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | Mar 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.