Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor
US7401211B2 · kind B2 · utility
3Cited by
6References
11Claims
0Family size
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Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jul 15, 2008 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can continue their execution. Several resources are used to reduce this unwanted impact of stalls on the non-stalling threads. Also, these resources ensure that the earlier stalled thread, now flushed, is re-executed when the data dependency is resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.