Bitline leakage limiting with improved voltage regulation
US7403439B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2006 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Oct 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit arrangements and methods are provided for regulating and maintaining voltage on bitlines of a semiconductor memory device. According to one embodiment, first and second regulation devices are connected to a charging circuit. At the beginning of a charging period, voltage on the bitlines is regulated with the second regulation device as the bitlines are initially charged to a voltage. After initially charging the bitlines to the voltage, voltage on the bitlines is regulated with the first regulation device that also limits current to the bitlines when there is a leakage anomaly associated with the bitlines. According to another embodiment, a charging circuit that is connected to sense nodes of a sense amplifier while the sense nodes are connected to the bitlines is activated so that the charging circuit assists in charging the bitlines at the beginning of a charging period. After the bitlines are initially charged at the beginning of the charging period, voltage on the bitlines is regulated with a first regulation device that regulates current to the bitlines and limits current to the bitlines when there is a leakage anomaly associated with the bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.