Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
US7404116B2 · kind B2 · utility
9Cited by
5References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2002 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Feb 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.