High efficiency, error minimizing coding strategy method and apparatus
US7404131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2001 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | Jan 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for creating a high efficiency, error minimizing code is provided. In addition, an apparatus having a high efficiency, error minimizing code is provided. In particular, the present invention provides a high efficiency, error minimizing code for use in connection with systems having a communication channel in which identifiable dominant errors occur, and that is used to transmit data that may be usefully applied in the system even though the received signal is not exactly equal to the original signal. Furthermore, the present invention provides a code that may be used to constrain the effects of dominant errors in a communication channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.