Fullchip functional equivalency and physical verification
US7404161B2 · kind B2 · utility
9Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2005 |
| Grant date | Jul 22, 2008 |
| Priority date | — |
| Expiry date | May 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived from symbolic connectivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.