Methods for forming co-planar wafer-scale chip packages
US7405108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2004 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Feb 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1433
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.