Lloyd Burrell
10Patents
5h-index
33Co-inventors
66Inventor score
Filing activity: Mar 12, 2001 → Sep 6, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6908841B2 | Support structures for wirebond regions of contact pads over low modulus materials | Electricity | 27 | Expired |
| US7250311B2 | Wirebond crack sensor for low-k die | Electricity | 20 | Expired |
| US6559042B2 | Process for forming fusible links | Electricity | 16 | Expired |
| US6960831B2 | Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad | Electricity | 14 | Expired |
| US7294565B2 | Method of fabricating a wire bond pad with Ni/Au metallization | Electricity | 8 | Expired |
| US7405108B2 | Methods for forming co-planar wafer-scale chip packages | Electricity | 5 | Expired |
| US7867820B2 | Methods for forming co-planar wafer-scale chip packages | Electricity | 3 | Active |
| US7037824B2 | Copper to aluminum interlayer interconnect using stud and via liner | Electricity | 2 | Expired |
| US7087997B2 | Copper to aluminum interlayer interconnect using stud and via liner | Electricity | 2 | Expired |
| US12334461B2 | Bonding structure using two oxide layers with different stress levels, and related method | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.