Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow
US7405116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Sep 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.