Circuit package and method of plating the same
US7405155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Mar 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09354
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.