Decoupled signal-power substrate architecture
US7405364B2 · kind B2 · utility
4Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | May 23, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device comprises a substrate core having power paths through it and an input/output signal routing layer upon the core substrate. An integrated circuit may be arranged on the routing layer such that the integrated circuit is electrically coupled to the substrate core through the routing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.