Stressed field effect transistors on hybrid orientation substrate

US7405436B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Dureseti Chidambarrao · Weston, US
• Judson R. Holt · Wappingers Falls, US
• Meikei Ieong · Wappingers Falls, US
• Oiging C. Ouyang · Yorktown Heights, US
• Siddhartha Panda · Beacon, US

Key dates

• Filing date: Jan 5, 2005
• Grant date: Jul 29, 2008
• Expiry date: Jan 20, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.