Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon
US7405450B2 · kind B2 · utility
2Cited by
22References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2004 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | May 18, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is on a sidewall of the gate line. A conductive line pattern is on the gate line. The conductive line pattern is parallel with the gate line and is electrically connected to the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.