Circuit for data bit inversion
US7405981B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Mar 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electric circuit for inverting a data bit of a data burst read out from a memory module comprises a buffer for buffering a data burst being comprised of at least two data words, a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously two neighbouring data words of the data words buffered in the buffer and generating an inversion flag, if the number of different data bits of the two neighbouring data words exceeds half the number of data bits of a data word, a correction device for generating a corrected inversion flag for a specific decoder of the decoders by inverting or not inverting the inversion flag of the specific decoder dependent on the inversion flag generated by the specific decoder and the inversion flags generated by the remaining of the decoders, and an inversion device comprised of a plurality of inverters, each inverting or not inverting a present of the data words of an associated of the decoders dependent on the corrected inversion flag of the associated decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.